include config.mk

VCS_CSRC_DIR = $(abspath ../../src/csrc)
VCS_CXXFLAGS += -std=c++11 -static -Wall -I$(VCS_CSRC_DIR) 
# VCS_LDFLAGS  += -lpthread -ldl -lz
VCS_LDFLAGS  += -Wl,--no-as-need -lpthread -lSDL2 -ldl -lz

VCS_FLAGS += -full64 +v2k -timescale=1ns/1ns -sverilog -debug_access+all +lint=TFIPC-L
VCS_FLAGS += +vcs+initreg+random # -P ${LD_LIBRARY_PATH}/novas.tab  ${LD_LIBRARY_PATH}/pli.a 
### CPU SEL
ifeq ($(CPU_SEL) , RenaCoreV1)
VCS_FLAGS += +define+RenaCoreV1
endif
ifeq ($(CPU_SEL) , RenaCoreV2)
VCS_FLAGS += +define+RenaCoreV2
endif
ifeq ($(CPU_SEL) , RenaCoreV3)
VCS_FLAGS += +define+RenaCoreV2
endif
### DPIC DDR
ifeq ($(USE_DPIC_DDR) , 1)
VCS_FLAGS += +define+USE_DPIC_DDR
endif
### Virtual Print
ifeq ($(VIRTUAL_PRINT) , 1)
VCS_FLAGS += +define+VIRTUAL_PRINT
endif
# VCS_FLAGS += +define+RANDOMIZE_DELAY=0  
# VCS_FLAGS += +define+START_ADDR="32'h3000_0000"
# C++ flags
VCS_FLAGS += -CFLAGS "$(VCS_CXXFLAGS)" -LDFLAGS "$(VCS_LDFLAGS)" -j4
VCS_FLAGS += -Mdir=build -Mupdate 

# 根据 BOOT_BIN 生成相应的ROM文件
boot:
	@ rm -f $(RENA_HOME)/hw/src/vsrc/peripheral/bootrom/gen/bootrom.bin
	@ ln -s $(BOOT_BIN) $(RENA_HOME)/hw/src/vsrc/peripheral/bootrom/gen/bootrom.bin
	@ make -C $(RENA_HOME)/hw/src/vsrc/peripheral/bootrom/gen bootrom.sv

vcs:boot
	@ mkdir -p build
	vcs $(VCS_FLAGS) -f filelist.f 

run:boot
	./simv +ddr=$(DDR_BIN) +sd=$(SD_BIN)

dump:boot
	./simv +ddr=$(DDR_BIN) +sd=$(SD_BIN) +dump-vcd

# -ucli -i dump.tcl

wave:
	gtkwave simv.vcd

# verdi:
# 	verdi -f filelist.f -ssf simv.fsdb &

all: vcs run

.PYHON:all

clean:
	rm -rf simv DVEfiles simv.daidir stack.info.* ucli.key $(VCS_BUILD_DIR)     \
	*.fsdb *.log verdiLog vc_hdrs.h novas.rc novas.*  build  simv.* vcdplus.vpd  
